Rambus is a premier chip and silicon IP provider seeking a Digital Verification Intern to join their Memory Interface Chips team. The Intern will work closely with experienced engineers to develop DDR memory interface products, executing verification plans and debugging issues.
Responsibilities
Create digital verification plans using datasheets, inputs from engineers/customers, and working closely with system and design engineers.
Implement digital test-benches in SystemVerilog and UVM to apply constrained random stimulus and checks.
Implement Systemverilog Assertions (SVA) to check digital DUT behavior.
Track bugs, functional coverage, and RTL code coverage
Work with design and systems teams to close bugs as they arise.
Qualification
Required
BS or MS in Electrical Engineering or Computer Engineering
Coursework: Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, Design and Analysis of Algorithms, Fundamentals of Machine Learning, Object Oriented Programming
High aptitude with Verilog and SystemVerilog
Advanced verification methodologies such as UVM
Python/ perl scripting
Familiarity with creating constrained-random stimulus and coverage based auto-checking verification environments
Preferred
Benefits
Competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership
Rambus designs, develops and licenses chip interface technologies and architectures that are used in digital electronics products.
